CMOS image sensor for suppressing degradation of spatial resolution and generating compressed image signals

ABSTRACT

The present invention is an image sensor having a pixel array, which arranges pixels having photoelectric conversion circuits in rows and columns; and a pixel selecting circuit for selecting each pixel, wherein the pixel selecting circuit selects pixels of all rows and/or pixels of all columns, and selects a pixel signal at every plural pixels among the selected pixel signals, and pixels selected from a pixel block of a plurality of rows and columns within the pixel array are dispersed within this pixel block.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a CMOS (complementary metal-oxidesemiconductor) image sensor, and more particularly to a CMOS imagesensor capable of preventing the degradation of spatial resolution whendecreasing pixels for a color image, and generating a compressed imagesignal.

2. Description of the Related Art

A CCD (charge-coupled device) sensor is used as an image sensor indigital still cameras and video tape recorders. A CCD sensor differsfrom an ordinary CMOS structure, and in line with this, requires afabrication process line with a degree of cleanness that is higher thanthe degree of cleanness for an ordinary CMOS LSI. Fabrication processline requirements such as this adversely affect the lowering of CCDsensor prices.

Meanwhile, attention is focusing on inexpensive versions of CMOS imagesensors in place of CCD sensors. A CMOS image sensor can be fabricatedvia an ordinary CMOS fabrication process, since the CMOS image sensorconstitutes a pixel using a photoelectric conversion circuit, which usesan MOS (metal-oxide semiconductor) transistor and a photodiode. As aresult of this, a CMOS image sensor can be fabricated by a semiconductorfabrication line of an ordinary degree of cleanness, and, in addition,an image signal detecting circuit, and an image processing circuitcomprising color processing can be formed on the same chip as an arrayof pixels, enabling a significant cost reduction compared to a CCDsensor. At present, the use of a CMOS image sensor as the image sensorof an inexpensive digital still camera has been proposed.

In a CMOS image sensor, RGB (red, green, blue) color filters aredisposed on top of chip pixels, and pixels corresponding to each ofthese colors output detection signals (pixel signals) corresponding tothe respective RGB gray scale values. Moreover, it is known thatoutputting more numerous detection signals of green (G), to which thehuman eye is most responsive, makes people highly sensitive, and anordinary pixel array is a Bayer Space, which constitutes odd rows, whichalternate red (R) and green (G), and even rows, which alternate blue (B)and green (G). In this array, green (G), which is the color for aluminance signal requiring high resolution, is arranged in a checkeredpattern, and red (R) and green (G), which are the remaining color, arearranged in a checkered pattern therebetween.

As a result of this, a detection signal outputted from a pixel array isan RGB mosaic signal in the order of RGRG . . . GBGB . . . . This RGBmosaic signal is converted to an RGB gray scale signal (RGB simultaneoussignal) for each pixel, and after a predetermined image processing, animage signal comprising an RGB gray scale signal corresponding to eachpixel is outputted.

In an image sensor such as this, when a compressed image signal isoutputted, the decreasing of a pixel signal is performed at a constantratio. For example, when an image is displayed on a relatively small LCD(liquid crystal display) display panel provided on a digital stillcamera or the like, because the number of pixels of the LCD displaypanel are less than the number of pixels of the image sensor, decreasingprocessing (sub-sampling processing) becomes necessary.

A method carried out for a CCD sensor is decreasing processing, whereinfixed pixel data is decreased after the A/D conversion of a pixel signaloutputted from a pixel array, and such a method is being pursued for aCMOS image sensor as well. Or, as another method, decreasing processingis also possible by simply decreasing an image signal after generatingan RGB simultaneous signal and performing color processing.

FIG. 1 is a diagram illustrating conventional decreasing for an RGBmosaic signal. In the pixel array 10, RGRG . . . pixels are arranged inthe odd numbered rows, and GBGB . . . pixels are arranged in the evennumbered rows. The pixel signals of each row are outputted to a columnline CL by driving a row selecting line ROW according to a verticalscanning circuit 12. The pixel signals outputted to a column line CL areheld by a sample-and-hold circuit SH provided for each column, and areoutputted from an output line 16 via column gates CG. Column gates CGare sequentially selected by column selection signals CS1-CS8 from acolumn selecting circuit 14, and pixel signals, which thesample-and-hold circuits SH of the respective columns are holding, aresequentially outputted.

Thus, pixel signals outputted from output line 16 are in the order ofRGRG . . . GBGB . . . , and by decreasing every two pixels from thesepixel signals, one-fourth of all the pixel signals are decreased. Thepixels enmeshed inside pixel array 10 of FIG. 1 are pixels correspondingto pixel signals, which are read out by decreasing processing.

However, the above-mentioned decreasing processing method requires thathardware for decreasing processing beadded to the stage subsequent to anA/D converter. The addition of such hardware adversely affects CMOSimage sensor cost-cutting.

Further, for the former decreasing processing, as shown in FIG. 1, anRGB mosaic signal is decreased at four pixels of two rows and twocolumns from among 16 pixels of four rows and four columns, andmoreover, four pixels adjacent to a corner within the 16 pixels areoutputted. A four-pixel RGB simultaneous signal is generated from theoutput RGGB pixel signals for these four pixels. As a result of this,the spatial resolution of a pixel signal subjected to decreasingprocessing deteriorates.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a CMOSimage sensor capable of performing decreasing processing of pixelsignals without increasing in hardware.

Further, another object of the present invention is to provide a CMOSimage sensor capable of performing decreasing processing of pixelsignals while suppressing the degradation of spatial resolution.

To achieve the above-mentioned objects, a first aspect of the presentinvention is an image sensor having a pixel array, which arrangespixels, having photoelectric conversion circuits, in rows and columns;and a pixel selecting circuit for selecting each pixel, wherein thepixel selecting circuit selects pixels of all rows and/or pixels of allcolumns, and selects a pixel signal at every plural pixels among theselected pixel signals, and pixels selected from a pixel block of aplurality of rows and columns within the pixel array are dispersedwithin this pixel block.

According to the above invention, a pixel selecting circuit, whichselects pixels of a pixel array, disperses selected pixels inside apixel block of a plurality of rows and columns, which is the smallestunit of decreasing processing, therefore, it is possible to suppress thedegradation of spatial resolution. That is, the pixel selecting circuitselects pixels such that the selected pixels are dispersed inside apixel block, which is the smallest unit of decreasing processing.Furthermore, since a pixel signal, which has already been decreased, issubjected to AD conversion, and outputted to an RGB simultaneous signalgenerating circuit or color processing circuit, it is possible to reducethe hardware circuits for decreasing processing.

To achieve the above-mentioned objects, a second aspect of the presentinvention is an image sensor having a pixel array, which arrangespixels, having photoelectric conversion circuits, in rows and columns; arow selecting circuit for selecting pixels in the row direction of thepixel array; sample-and-hold circuits for holding pixel signalsoutputted from the pixel array; and a column selecting circuit forselecting pixel signals being held by these sample-and-hold circuits,wherein the sample-and-hold circuits average pixel signals of the samecolor, which are close to one another in the row direction and/or columndirection of the pixel array.

According to the above invention, the average to pixel signals beingheld by the sample-and-hold circuits is taken between same color pixelsbeing close each other, and these averaged pixel signals are outputted.Therefore, although an outputted pixel signal has a resolution, whichhas been decreased at a constant ratio, the original pixel signal forgenerating this pixel signal has higher spatial resolution.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating decreasing processing for aconventional RGB mosaic signal;

FIG. 2 is a block diagram of an entire CMOS image sensor in an aspect ofthe embodiment;

FIG. 3 is a diagram showing a photoelectric conversion circuit inside apixel, and a sample-and-hold circuit for each column;

FIG. 4 is a diagram showing selected pixels in a first aspect of theembodiment;

FIG. 5 is a diagram showing an example of a column selecting circuit andthe operation thereof;

FIG. 6 is a diagram showing pixel signals outputted to output line 16,and line memory operation relative thereto in the first aspect of theembodiment;

FIG. 7 is a block diagram of an image sensor showing an example of avariation of the first aspect of the embodiment;

FIG. 8 is a block diagram of an image sensor of a second aspect of theembodiment;

FIG. 9 is a diagram showing a detailed circuit diagram ofsample-and-hold circuits in the second aspect of the embodiment;

FIG. 10 is a diagram showing pixel selection in a third aspect of theembodiment;

FIG. 11 is a detailed circuit diagram of sample-and-hold circuits SH inthe third aspect of the embodiment;

FIG. 12 is a block diagram of an image sensor of a fourth aspect of theembodiment;

FIG. 13 is a diagram illustrating the operation of sample-and-holdcircuits in the fourth aspect of the embodiment;

FIG. 14 is a block diagram of an image sensor in a fifth aspect of theembodiment;

FIG. 15 is a block diagram of an image sensor in a sixth aspect of theembodiment;

FIG. 16 is a diagram showing the operation of sample-and-hold circuitsin the sixth aspect of the embodiment; and

FIG. 17 is a circuit diagram indicating the reduced power dissipation ofsample-and-hold circuits.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The embodiment of the present invention will be explained hereinbelow byreferring to the figures. However, the scope of protection of thepresent invention is not limited to the aspects of the embodimenthereinbelow, but rather extends to the inventions disclosed in theclaims, and to the equivalents thereof.

FIG. 2 is a block diagram of an entire CMOS image sensor in anembodiment. The image sensor shown in the figure has a pixel array 10,in which pixels, each having a photoelectric conversion circuit, arearranged in rows and columns; a row selecting circuit 12 for selectingpixels in the row direction; sample-and-hold circuits SH for holdingpixel signals outputted to a column line from a selected pixel; and acolumn selecting circuit 14 for selecting pixel signals being held insample-and-hold circuits SH, and outputting same to an output line 16.

An analog pixel signal is outputted to output line 16, amplified by anamplifier 20, and converted to a digital pixel signal (pixel data) by ananalog-to-digital converter 22. As will be explained hereinbelow, apixel array 10 is constituted such that pixel signals of RGRG . . . aredetected in the odd numbered rows, and pixel signals of GBGB . . . aredetected in the even numbered rows. Therefore, the output signal S22 ofAD converter 22 is an RGB mosaic signal.

An output image signal S28 outputted from the image sensor must have RGBgray scale data for each pixel. Thus, RGB mosaic signal S22 is convertedto an RGB simultaneous signal S24 (a signal having RGB gray scale datafor each pixel) by a simultaneous signal converter 24. An RGBsimultaneous signal S24 is determined from the RGB mosaic signals ofpixels surrounding the pixel targeted for determination. Thus, in theexample of FIG. 2, mosaic signals for three rows are supplied to thesimultaneous signal converter 24. Therefore, line memories 26A, 26B forstoring one row's worth of mosaic signals S22 are provided. Two rows'worth of mosaic signals are supplied from these two line memories 26A,26B, and the mosaic signal S22 of the final third row is supplied fromAD converter 22.

A thus determined RGB simultaneous signal S24 for each pixel issubjected to color processing, such as color adjustment, edgeenhancement processing, and gamma correction, by a subsequent-stageimage processing circuit 28, and outputted as an output image signalS28.

FIG. 3 is a diagram showing a photoelectric conversion circuit inside apixel, and a sample-and-hold circuit for each column. In the figure, thepixels P11-P22 of two rows and two columns are shown, and aphotoelectric conversion circuit inside a pixel is shown only for pixelP11.

In the photoelectric conversion circuit inside the pixel, a resettransistor N1, an amplifier transistor N2, and a selection transistor N3are provided relative to a photodiode PD, which is a photoelectricconverting device. By the row selecting circuit 12 driving a reset lineRST, the reset transistor N1 becomes conductive, and a connecting nodenpd with the photodiode PD is pre-charged to the power source Vcc level.When the reset transistor N1 becomes nonconductive, a currentcorresponding to an amount of light being received is generated by thephotodiode PD, and the electric potential of the node npd is reduced bythis current. Then, after a fixed light receiving period, when the rowselecting circuit 12 drives a row line ROW1, causing the selectiontransistor N3 to become conductive, a signal of electric potentialamplified by transistor N2 is outputted to a column line CL1. A sourceof current transistor N4 is connected to column line CL1.

Next, sample-and-hold circuits SH1, SH2 connected to each column lineCL1, CL2 will be explained. Sample-and-hold circuits SH1, SH2 shown inthe figure are examples of CDS (Correlated Double Sampling) circuits. ACDS circuit has a capacitor Csh for holding an analog image signaloutputted to a column line CL1, CL2. And analog amplifiers 30, 34 aredisposed before and after the capacitor Csh, respectively.

Furthermore, to remove undesired noise, a capacitor Csh holds a voltagedifferential of a reset level and a detection level. Thus, when thephotoelectric conversion circuit of a pixel is reset, the reset level isheld in the capacitor Csh. At that time, a reference voltage Vref isapplied to an electrode on the opposite side of the capacitor Csh via areset switch 32. As a result of this, a voltage of Vref−Vr (Vr being thereset level) is held in the capacitor Csh.

Next, a received-light signal Vn, which the electric potential reducesin accordance with the amount of received light, is applied to acapacitor Csh after the light-receiving period. Reset switch 32 is inthe open state at this time, and consequently, Vref−Vr+Vn=Vref−(Vr−Vn)is applied to the capacitor Csh. Undesired noise is removed by this(Vr−Vn), and a pixel signal corresponding to the amount of receivedlight is outputted by amplifier 34.

Pixel signals, which sample-and-hold circuits SH1, SH2 cause to be heldby capacitors Csh, are outputted to output line 16 via column gates CG1,CG2. Thus, column selecting circuit 14 drives column selection signalsCS1, CS2 in succession, and causes column gates CG1, CG2 to conduct insequence. As a result of this, pixel signals detected for pixels of thesame row are outputted from output line 16 in time sequence.

FIG. 4 is a diagram showing selected pixels in a first aspect of theembodiment. FIG. 4 shows enmeshed pixels selected as a result of quarterdecreasing processing. In a pixel, which generates an RGB mosaic signal,for quarter decreasing, it is necessary to select one red (R) pixel, twogreen (G) pixels and one blue (B) pixel from a pixel block PBLKcomprising 16 pixels of four rows and four columns, which is thesmallest unit of decreasing processing. Accordingly, in this aspect ofthe embodiment, the first R pixel in the first row, the third G pixel inthe second row, the second G pixel in the third row, and the fourth Bpixel in the fourth row are selected in the pixel block PBLK. These fourselected pixel signals constitute an RGGB mosaic signal. However, thefour selected pixels are dispersed inside the pixel block PBLK. Thus,the spatial resolution of the outputted RGB mosaic signal is higher thanthe conventional example of FIG. 1.

As described hereinabove, in order to select four pixels of dispersedlocations inside a pixel block PBLK, which is the smallest unit ofdecreasing processing, column selecting circuit 14 generates columnselection signals CS1-CS8 differently from an ordinary operation whendecreasing processing is not performed. That is, when row selectingcircuit 12 selects pixels of the first row, from among thesample-and-hold circuit-held pixel signals, only the first column andfifth column are selected from column gates CG1, CG5, and are outputtedsequentially to output line 16. Thus, column selecting circuit 14sequentially drives column selection signals CS1, CS5. As a result ofthis, the pixel signals of the first row all constitute R pixel signals.

FIG. 5 is a diagram showing an example of a column selecting circuit andthe operation thereof. Column selecting circuit 14 comprises a shiftregister comprising flip-flops FF0, 1, 2 for transmitting an H level inaccordance with a clock CLK, and an OR gate group 36, which drivescolumn selection signals CS1-CS8 by OR operations of flip-flop outputsand phase signals ph0-ph3. According to an operation in the first phaseperiod shown in FIG. 5B, only phase signal ph0 is driven to H level, andthe remaining phase signals ph1-ph3 constitute L level. In this state,by the shift register shifting to H level in synchronization with clockCLK, column selection signals CS1, CS5 are driven in sequence.

Returning to FIG. 4, when row selecting circuit 12 selects pixels of thesecond row, only the third column and the seventh column are selectedfrom column gates CG3, CG7, and G pixel signals are outputted to outputline 16 in sequence. In the column selecting circuit 14 of FIG. 5, onlyphase signal ph2 transitions to H level, and the shift register shiftsto H level in synchronization with clock CLK. As a result of this,column selection signals CS3, CS7 are driven in sequence.

When row selecting circuit 12 selects pixels of the third row, only thesecond column and the sixth column are selected, and G pixel signals areoutputted to output line 16 in sequence. Furthermore, when row selectingcircuit 12 selects pixels of the fourth row, only the fourth column andthe eighth column are selected, and B pixel signals are outputted tooutput line 16 in sequence.

In this manner, according to the operations of row selecting circuit 12and column selecting circuit 14 in line with decreasing processing, rowselecting circuit 12 drives the row lines ROW sequentially, and selectspixels of each row in order, and column selecting circuit 14 drivescolumn selection signals CG1-CG4 such that all of the columns inside apixel block PBLK are selected, and one R pixel, two G pixels and one Bpixel are selected. As a result of this, the signals of four pixelsdispersed inside a pixel block PBLK are selected and outputted.

FIG. 6 is a diagram showing pixel signals outputted to output line 16,and line memory operation relative thereto in the first aspect of theembodiment. As described hereinabove, red (R) pixel signals R11, R13,R15, R17 are outputted from the first row of pixels every four cycles ofa horizontal clock HCLK. The numbers of these pixel signals indicate thesequence of the pixels ultimately decreased and read out. In line withthe readout thereof, readout pixel signals R11, R13, R15, R17 arewritten to an odd-numbered address of line memory 26A, which is providedin the stage prior to simultaneous signal converter 24.

Next, green (G) pixel signals G12, G14, G16, G18 are outputted from thesecond row of pixels, and written to an even-numbered address of linememory 26A. Pixel signals of line memory 26A are shifted to another linememory 26B, and green (G) pixel signals G21, G23, G25, G27, which wereoutputted from the third row of pixels, are written to an odd-numberedaddress of line memory 26A. Furthermore, blue (B) pixel signals B22,B24, B26, B28 outputted from the fourth row of pixels are written to aneven-numbered address of line memory 26A.

As described hereinabove, an RGRGRG mosaic signal is written to linememory 26B, and a GBGBGB mosaic signal is written to line memory 26A,respectively.

FIG. 7 is a block diagram of an image sensor, showing a variation of thefirst aspect of the embodiment. FIG. 7 differs from FIG. 4 in that agroup of switches 38 for column selection are disposed between the pixelarray 10 and the sample-and-hold circuits SH. This group of columnselection switches 38 is controlled by pre-stage column selectionsignals CSP from column selecting circuit 14.

According to this variation, when a pixel array of the first row isselected, only R pixel signals of the first columns inside pixel blockPBLKs are held in sample-and-hold circuits SH1, SH5 via column selectionswitches SW1, SW5. Next, when the pixel array of the second row isselected, only G pixel signals of the third columns inside pixel blockPBLKs are held in sample-and-hold circuits SH3, SH7 via column selectionswitches SW3, SW7. Thereafter, RGRGRG mosaic signals held insample-and-hold circuits SH are sequentially outputted to output line 16via column gates CG1, CG3, CG5, CG7 by column selection signals CS1,CS3, CS5, CS7 from column selecting circuit 14.

Similarly, when the pixel array of the third row is selected, only Gpixel signals of the second columns inside pixel blocks PBLK are held insample-and-hold circuits SH, and when the pixel array of the subsequentfourth row is selected, B pixel signals of the fourth columns insidepixel blocks PBLK are held. And thereafter, GBGBGB mosaic signals aresequentially outputted to output line 16 from even-numbered column gatesCG.

According to the above variation, R pixel signals of the first row ofpixel array are held one time by sample-and-hold circuits SH, and Gpixel signals of the pixel array of the subsequent second row are heldby sample-and-hold circuits SH, and thereafter, these RGRGRG pixelsignals are outputted to output line 16. Consequently, the pixel signalsoutputted to this output line 16 are the same as RGRGRG mosaic signalsof an ordinary readout. Therefore, it is possible for a subsequent stagecircuit to generate an RGB simultaneous signal by the same operation asan ordinary readout.

In the first aspect of the embodiment, according to another method forselecting pixels inside a pixel block PBLK, a G pixel of the fourthcolumn is selected in the first row, a B pixel of the second column isselected in the second row, an R pixel of the third column is selectedin the third row, and a G pixel of the first column is selected in thefourth row. Or, in another pixel selection method, an R pixel of thethird column is selected in the first row, a G pixel of the first columnis selected in the second row, a G pixel of the fourth column isselected in the third row, and a B pixel of the second column isselected in the fourth row. Furthermore, in another pixel selectionmethod, a G pixel of the second column is selected in the first row, a Bpixel of the fourth column is selected in the second row, an R pixel ofthe first column is selected in the third row, and a G pixel of thethird column is selected in the fourth row. By performing the aboveselections, all of the rows and columns inside a pixel block can beselected, and the pixel signals, which are read out, can be dispersedinside the pixel block.

FIG. 8 is a block diagram of an image sensor in a second aspect of theembodiment. In the second aspect of the embodiment, in order to decreasethe pixel signals to a quarter of all, pixel signals decreased to a halfare read out from pixel array 10, the averages of pixel signals of thesame color, which are close to one another in the row direction, aretaken, and in the end, one-fourth of the decreased pixel signals areoutputted. Thus, the image sensor of FIG. 8 differs from that of FIG. 4in that one-third selectors 40 are disposed between pixel array 10 andsample-and-hold circuits SH, and furthermore, as will be explainedhereinbelow, switches for generating averages are disposed betweenadjacent columns inside sample-and-hold circuits SH. The one-thirdselectors 40 are controlled by control signals CSP, and average switchesinside sample-and-hold circuits SH are controlled by control signalsCSQ.

In the pixel selection method in the second aspect of the embodiment, asshown in FIG. 8, all the R pixel signals in the pixel array of the firstrow are read out, averaging is performed between adjacent R pixels inthe sample-and-hold circuits SH, and the one-fourth decreased R pixelsignals are outputted. Further, all the G pixel signals in the pixelarray of the second row are read out, averaging is performed in the sameway by the sample-and-hold circuits SH, and the one-fourth decreased Gpixel signals are outputted. At this point in time, the RGRG pixelsignals being held in the sample-and-hold circuits are outputted tooutput line 16 from column gates. Similarly, all G pixel signals in thepixel array of the third row are read out, and averaging is performedbetween adjacent pixels, and all B pixel signals in the pixel array ofthe fourth row are readout, and averaging is performed between adjacentpixels. Thereafter, the GBGB pixel signals being held in thesample-and-hold circuits are outputted to output line 16 from columngates.

FIG. 9 is a diagram showing a detailed circuit diagram ofsample-and-hold circuits in the second aspect of the embodiment.Further, in FIG. 9, the constitution of a selector SEL is also shown. Ina selector SEL, three switches SW1, 2, 3 are provided for selectivelyconnecting the same column and the columns of both sides to asample-and-hold circuit SH. Then, one of the switches can be closed by acontrol signal CSP, and one of the three columns is supplied toamplifier 30 of a sample-and-hold circuit SH. Further, a sample-and-holdcircuit SH is the same as the circuit shown in FIG. 3, and a switches 42are added to generate an average between adjacent columns. Theseswitches 42 are controlled by control signal CSQ.

The method for selecting pixel signals in the second aspect of theembodiment will be explained by referring to FIG. 8 and FIG. 9. Rowselecting circuit 12 sequentially selects rows of pixel array 10. Whenthe first row is selected, the switch SW2 of the first column selectorSEL conducts, so that the R pixel signal of the first column is held inthe capacitor of sample-and-hold circuit SH1 of the first column, andthe switch SW3 of the third column selector SEL conducts, so that the Rpixel signal of the third column is held in the capacitor ofsample-and-hold circuit SH2 of the second column. The operation is thesame for the fifth column and the seventh column as well. The selectorsSEL of the third, fourth, seventh and eighth columns are in thenon-conductive state as-is. Thereafter, in response to a control signalCSQ, the averaging switch 42 between the first column and the secondcolumn, and the averaging switch 42 between the fifth column and thesixth column conduct, and the averages of two R pixel signals are heldin the holding capacitors Csh of the first column and the fifth column,respectively.

Next, when the second row is selected, this time the switch SW3 of thesecond column selector SEL conducts, so that the G pixel signal of thefirst column is held in the capacitor of sample-and-hold circuit SH2 ofthe second column, and the switch SW2 of the third column selector SELconducts, so that the G pixel signal of the third column is held in thecapacitor of sample-and-hold circuit SH3 of the third column. Theoperation is the same for the selectors SEL of the sixth column and theseventh column as well. Thereafter, the switches 42 between the secondand third columns, and between the sixth and seventh columns conduct,and the averages of two G pixel signals are held in the holdingcapacitors Csh of the third column and the seventh column, respectively.

Thereafter, column selecting circuit 14 drives odd-numbered columnselection signals CS1, 3, 5, 7, and the pixel signals stored insample-and-hold circuits SH1, 3, 5, 7 of the first, third, fifth andseventh columns are sequentially outputted to output line 16. Therefore,signals outputted to output line 16 are RGRG mosaic signals.

When the third row is selected, G pixel signals of the second, fourth,sixth and eighth columns are held in sample-and-hold circuits of thesecond and third columns, and sixth and seventh columns, and averaged Gpixel signals are held in sample-and-hold circuits SH2, 6 of the secondand sixth columns. Furthermore, when the fourth row is selected, B pixelsignals of the second, fourth, sixth and eighth columns are held insample-and-hold circuits of the third and fourth columns, and seventhand eighth columns, and averaged B pixel signals are held insample-and-hold circuits SH4, 8 of the fourth and eighth columns.Thereafter, column selecting circuit 14 drives even-numbered columnselection signals CS2, 4, 6, 8, and a GBGB mosaic signal is outputted tooutput line 16.

In the second aspect of the embodiment, even though the pixels aredecreased to a quarter of all, pixel signals which have been decreasedto a half are read out from the pixel array, and averaging of pixelsignals of the same color, which are adjacent to one another in the rowdirection, is performed by sample-and-hold circuits SH. Furthermore,because two rows of pixel signals are combined and read to output line16 from column gates CG, it is possible to output the same RGRG . . .GBGB . . . mosaic signals as an ordinary readout. Thus, an RGBsimultaneous signal can be generated via the same processing as anordinary readout.

FIG. 10 is a diagram showing pixel selection in a third aspect of theembodiment. In the third aspect of the embodiment, in order to decreasepixels to a quarter of all, pixels decreased to a half are read out froma pixel array 10, the averages of pixel signals of the same color, whichare close to one another in the column direction, are taken, andone-fourth of the decreased pixel signals are ultimately outputted.Thus, in the image sensor of FIG. 10, the row selecting circuit 12selects pixels of the pixel array in the order of the first row, thirdrow, second row, and fourth row, as indicated by the arrows. And, aswill be explained hereinbelow, holding capacitors are disposed inparallel inside the sample-and-hold circuits SH, and the averages ofpixel signals of the same color, which are adjacent to one another inthe column direction, are generated.

FIG. 11 is a detailed circuit diagram of sample-and-hold circuits SH inthe third aspect of the embodiment. As shown in the figure, two columnseach of holding capacitors Csh are disposed in parallel in thesample-and-hold circuit of each column, and switch 44 of the stage priorthereto supplies pixel signals of the same color, which are adjacent toone another in the column direction, to holding capacitors Csh1, Csh2,respectively. Since these parallel holding capacitors Csh1, 2 areconnected to electrodes of the opposite side, an average value of twopixel signals adjacent to one another in the column direction can besupplied to subsequent-stage amplifier 34.

The method of selecting pixels in the third aspect of the embodimentwill be explained in accordance with FIGS. 10, 11. First, row selectingcircuit 12 selects the pixel array of the first row, and one holdingcapacitor Csh1 of sample-and-hold circuits SH1, 2, 5, 6 of the first andsecond columns, and the fifth and sixth columns hold R pixel signals andG pixel signals, respectively. Next, row selecting circuit 12 selectsthe pixel array of the third row, and similarly, the other holdingcapacitors Csh2 of sample-and-hold circuits SH1, 2, 5, 6 of the firstand second columns, and the fifth and sixth columns hold R pixel signalsand G pixel signals, respectively. As a result of this, averaged R pixelsignals and G pixel signals are held in these sample-and-hold circuitsSH1, 2, 5, 6.

Thereafter, by column selecting circuit 14 sequentially driving columnselection signals CS1, 2, 5, 6, RGRG mosaic signals which have beendecreased to a quarter are outputted to output line 16.

Next, row selecting circuit 12 selects the pixel array of the secondrow, and one holding capacitors Csh1 of sample-and-hold circuits SH3, 4,7, 8 of the third and fourth columns, and the seventh and eighth columnshold G pixel signals and B pixel signals, respectively. Next, rowselecting circuit 12 selects the pixel array of the fourth row, andsimilarly, the other holding capacitors Csh2 of sample-and-hold circuitsSH3, 4, 7, 8 of the third and fourth columns, and the seventh and eighthcolumns hold G pixel signals and B pixel signals, respectively. As aresult of this, averaged G pixel signals and B pixel signals are held inthese sample-and-hold circuits, and thereafter, these pixel signals GBGB. . . are outputted to output line 16 by column selecting circuit 14.This GBGB . . . pixel signal is the same as a mosaic signal.

In the third aspect of the embodiment, too, in order to decrease pixelsignals to a quarter, pixel signals which have been decreased to a halfare read out, and the averages of same color pixel signals adjacent toone another in the column direction are taken. And then, by making useof the hold function of the sample-and-hold circuits, RGB mosaicsignals, which are the same as ordinary readouts, are outputted tooutput line 16. As a result of this, a subsequent-stage circuit fordetermining an RGB simultaneous signal can be the same circuit as atordinary readout. And because pixel signals are read out after havingbeen decreased to a half, the spatial resolution of the pixel signalscan be improved.

FIG. 12 is a block diagram of an image sensor in a fourth aspect of theembodiment. In the fourth aspect of the embodiment, the averages ofpixel signals of the same color, which are adjacent to one another inthe column direction, are generated, and, in addition, the averages ofpixel signals of the same color, which are adjacent to one another inthe row direction, are also generated. In other words, the second aspectof the embodiment has been applied to the third aspect of theembodiment. As for the sample-and-hold circuits SH for this, as shown inFIG. 11, the sample-and-hold circuits of each column have parallelholding capacitors for holding pixel signals, which are adjacent to oneanother in the column direction, and, in addition, switches, whichinterconnect the capacitors of the first and third columns, second andfourth columns, fifth and seventh columns, and sixth and eighth columns,are provided for averaging pixel signals, which are adjacent to oneanother in the row direction. Control of the switches inside thesample-and-hold circuits is performed by control signals CSQ generatedby column selecting circuit 14.

FIG. 13 is a diagram illustrating the operation of sample-and-holdcircuits in the fourth aspect of the embodiment. In FIG. 13, the pixelsignals held in each of the sample-and-hold circuits SH1, 2, 3, 4 of thefirst-fourth columns when a row ROW is selected, and the pixel signalsto be averaged, are indicated by arrows.

Row selecting circuit 12 selects pixel arrays in the order of the first,third, second, fourth, fifth, seventh, sixth and eighth rows in the samemanner as in the third aspect of the embodiment. First, the pixel arrayof the first row is selected, and pixel signals R1, G12, R13, G14 of thefirst-fourth columns are held in the one side holding capacitors of therespective sample-and-hold circuits SH1-SH4. Next, the pixel array ofthe third row is selected, and pixel signals R31, G32, R33, G34 of thefirst-fourth columns are held in the other side holding capacitors ofthe respective sample-and-hold circuits SH1-SH4. As a result of this,the averages of same-color pixel signals adjacent to one another in thecolumn direction are generated in the same manner as in the third aspectof the embodiment. Thereafter, the switch between the first and thirdcolumns, and the switch between the second and fourth columns conduct,the average of the R pixel signals of the first column and third columnis generated, and the average of the G pixel signals of the secondcolumn and fourth column is generated. As a result of this, after thepixel array of the third row has been selected, an RG mosaic signal isread out from output line 16. This mosaic signal has been decreased to aquarter, but because it is generated from all of the pixel signals,spatial resolution is higher.

Next, the pixel array of the second row is selected, and the pixel arrayof the fourth row is selected, and the average of same-color pixelsignals adjacent to one another in the column direction, and the averageof same-color pixel signals adjacent to one another in the row directionare generated. As a result of this, after the pixel array of the fourthrow has been selected, a GB mosaic signal is read out from output line16.

Similarly, after the pixel arrays of the fifth and seventh rows havebeen selected, an RG mosaic signal is outputted, and after the pixelarrays of the sixth and eighth rows have been selected, a GB mosaicsignal is outputted, respectively.

In the fourth aspect of the embodiment, all the pixel signals are used,and a mosaic signal, which has been decreased to a quarter by anaveraging process, can be outputted.

FIG. 14 is a block diagram of an image sensor in a fifth aspect of theembodiment. In this aspect, row selecting circuit 12 sequentiallyselects the first and second rows, and the fifth and sixth rows, andafter the respective rows have been selected, averaging between thefirst and third columns, averaging between the second and fourthcolumns, averaging between the fifth and seventh columns, and averagingbetween the sixth and eighth columns, respectively, are carried out inthe sample-and-hold circuits SH as illustrated by the arrows in thefigure. In other words, in the row direction, adjacent same-color pixelsignals are averaged inside sample-and-hold circuits, and decreased to ahalf, and in the column direction, pixel signals are decreased to a halfby row selecting circuit 12 selecting pixel arrays at intervals.

In the fifth aspect of the embodiment, each time a row is selected,same-color pixel signals, which are adjacent in the row direction, areaveraged in sample-and-hold circuits, and outputted from output line 16.Consequently, when the first row is selected, an RGRG mosaic signal isoutputted from output line 16, and when the second row is selected, aGBGB mosaic signal is outputted from output line 16. Furthermore, whenthe fifth row is selected, an RGRG mosaic signal is outputted, and whenthe sixth row is selected, a GBGB mosaic signal is outputted,respectively. In the fifth aspect of the embodiment, row selection isdone at intervals, but all pixels in the column direction are selected.

FIG. 15 is a block diagram of an image sensor in a sixth aspect of theembodiment. In this aspect, black-and-white pixel signals are decreasedto a quarter and read out. For a black-and-white image sensor, a colorfilter, which differs for each pixel, is not provided, and pixel signalscorresponding to the black-and-white gray scale are generated in allpixels of pixel array 10.

In the sixth aspect of the embodiment, all pixel signals are read out,and according to circumstances, the average of pixel signals, which areadjacent in the row direction, is generated by sample-and-hold circuitsSH, average values for two rows are held inside the respectivesample-and-hold circuits SH, and after two rows of pixel array 10 havebeen read out, pixel signals held inside sample-and-hold circuits SH areoutputted to output line 16 via column gates CG. Therefore, each timetwo rows are selected, pixel signal which have been decreased to a halfis outputted from output line 16. As a result of this, a pixel signalwhich has been decreased to a quarter is outputted.

The constitution of a sample-and-hold circuit SH is the same as theexample of FIG. 9, but control of the group of switches 42 forconnecting capacitor electrodes between columns differs from that of thesecond aspect of the embodiment.

FIG. 16 is a diagram showing the operation of sample-and-hold circuitsin the sixth aspect of the embodiment. When row selecting circuit 12selects the first row of the pixel array, pixel signals P11, P12, P15,P16 of the first, second, fifth and sixth columns are held insample-and-hold circuits SH1, SH2, SH5, SH6. Thereafter, switches 40between the first and second columns, and fifth and sixth columnsconduct, the averages of pixel signals held in these columns aregenerated, and are held by sample-and-hold circuits SH1, SH5 of thefirst column and the fifth column, respectively. Next, when the secondrow of pixel array is selected, pixel signals of the third and fourthcolumns are held in sample-and-hold circuits SH3, SH4. Thereafter,switches 40 between the third and fourth columns conduct, and theaverages of pixel signals held in these columns are generated. In themeantime, sample-and-hold circuits SH1, SH5 of the first column and thefifth column hold pixel signals. Then, pixel signals held inodd-numbered column sample-and-hold circuits are outputted to outputline 16 via column gates.

Similarly, when the third row of the pixel array is selected, pixelsignals of the second and third columns, and the sixth and seventhcolumns are held in sample-and-hold circuits SH2, SH3, SH6, SH7, theswitches 40 therebetween conduct, and the averages of the pixel signalsheld in these columns are generated. Then, these averages are held bysample-and-hold circuits SH2, SH6 of the second column and the sixthcolumn. Similarly, the fourth row of the pixel array is selected, andthe averages of pixel signals of the fourth and fifth columns are heldin sample-and-hold circuit SH4 of the fourth column. Thereafter, pixelsignals being held by sample-and-hold circuits of even-numbered columnsare sequentially outputted.

In the sixth aspect of the embodiment, there are black-and-white pixelsignals, all pixels are read out, the averages of pixel signals, whichare adjacent to one another within the same row, are taken, and theseaveraged pixel signals are outputted from sample-and-hold circuits everytwo rows. As a result of this, it is possible to output decreased pixelsignals, which have been decreased to a quarter and have high spatialresolution.

FIG. 17 is a circuit diagram showing the reduced power dissipation ofsample-and-hold circuits. In FIG. 17, a column-direction pixel PX, acolumn line CL, and a sample-and-hold circuit SH are shown. For the sakeof simplicity, two pixels PX1, 2, two column lines CL1, 2, two detailedsample-and-hold circuits SH1, SH2, and abridged sample-and-hold circuitsSH3, SH4 are shown.

Pixels PX1, PX2 are the same as the example of FIG. 3. Further, a sourceof current transistor N4 and a switching transistor N5 for the source ofcurrent are provided in column lines CL1, CL2. Further, eachsample-and-hold circuit SH1, 2 is constituted from a pre-stage amplifier30 constituting a switching transistor N6 for activation, a transistorN7 for amplification, and a transistor N8 for a source of current, apost-stage amplifier 34 constituting a switching transistor N9 foractivation, a transistor N10 for amplification, and a transistor N11 fora source of current, a capacitor Csh for holding, and a reset switch 32.

Now then, current source switching transistor N5, and activationswitching transistors N6, N9 of amplifiers 30, 34 are connected to powercontrol signals PC1-PC4 corresponding thereto. Power control signalsPC1-PC4 are driven to H level for columns required for sampling andholding pixel signals. For example, when power control signal PC1 isdriven to H level, current source switch N5 of the column line of thefirst column conducts, pre-stage amplifier 30(1) and post-stageamplifier 34(1) of sample-and-hold circuit SH1 are activated, and apixel signal is sampled. In this case, reset switch 32 is also driven ata prescribed timing in accordance with power control signal PC1.Furthermore, when power control signal PC2 is driven to H level, thesame switching transistor of the second column conducts, and activationoccurs.

Accordingly, in the aspect of the embodiment described hereinabove, in adecreasing operation, a power control signal is controlled to L levelas-is for a column for which operation is not required. As a result ofthis, power consumption can be reduced for that column. For example, inthe first aspect of the embodiment of FIG. 4, when the pixel array ofthe first row is selected, since the sample-and-hold circuits of thefirst column and fifth column can be operated, only power control signalPC1 is driven to H level, and the remaining three power control signalsPC2-PC4 constitute L level as-is.

Or, in the case of the third aspect of the embodiment of FIG. 10, whenthe first row of the pixel array is selected, since the sample-and-holdcircuits of the first and second columns, and fifth and sixth columnsshould be operated, only power control signals PC1, PC2 are driven to Hlevel, and the remaining two power control signals PC3, PC4 constitute Llevel as-is. Similarly, when the second row of the pixel array isselected, the power control signals are controlled to the reversedpolarity of that described hereinabove.

Furthermore, in the case of the sixth aspect of the embodiment of FIG.15, when the pixels of the first row are selected, power control signalsPC1, PC2 are driven to H level for the first, second, fifth and sixthcolumns, and the power control signals PC3, PC4 for the third and fourthcolumns constitute L level as-is. Further, when the pixels of the thirdrow are selected, power control signals PC2, PC3 are driven to H levelfor the second, third, sixth and seventh columns, and power controlsignals other than these are L level.

As explained hereinabove, a CMOS image sensor of the first aspect of theembodiment can prevent the degradation of spatial resolution in adecreased readout by using sample-and-hold circuits and column gates foramplifying and outputting pixel arrays and the pixel signals thereof.That is, by the operation of the row selecting circuit and the columnselecting circuit, it is possible to spatially disperse pixel signalsdecreased and read out from a pixel array. When a pixel array isarranged in accordance with a Bayer Space (checkered pattern), it ispossible to sequentially read out an RGB mosaic signal from spatiallydispersed pixels.

Furthermore, in the second and subsequent aspects of the embodiment, theaverages of pixel signals, which are either adjacent or close to oneanother, are determined and held until the optimal timing bysample-and-hold circuits, and sequentially read out from column gates,thereby enabling the output of an RGB mosaic signal, which has beendecreased using more pixel signals. For example, when pixel signals aredecreased to a quarter and read out, since pixel signals decreased frommore numerous pixel signals are generated, the degradation of spatialresolution is prevented.

Furthermore, in the above aspects of the embodiment, the scanningdirections of the row selecting circuit and column selecting circuit arehorizontal direction from left to right, and vertical direction from topto bottom. However, even if the respective scanning directions are fromright to left, and from bottom to top, it is possible to perform thesame control as that of the aspects of the embodiment. Further, when thescanning direction is capable of being switched as needed, and it ispossible to display a mirror-inverted image, the same control as that inthe above aspects of the embodiment can be performed for the respectiveswitched scanning directions.

Further, in the above aspects of the embodiment, explanations were givenusing examples in which RGB pixels were arrayed. However, the presentinvention is not limited thereto, and the same control can also beapplied to an image sensor in which RGB, and CMY (cyan, magenta,yellow), which is a complementary color relationship, are arranged in apredetermined array. For example, the same decreasing mode readout canbe performed even when odd-numbered rows make use of complementary colorfilters, by which pixels are arrayed in the order of MGMG, andeven-numbered rows make use of complementary color filters, by whichpixels are arrayed in the order of CYCY.

Furthermore, when RGB primary color filters are used, the presentinvention can also be applied when using an interlaced Bayer array, inwhich, two rows of RGRG and two rows of GBGB are each alternatelyarrayed.

According to the present invention explained hereinabove, an imagesensor, which uses CMOS circuitry, is capable of suppressing thedegradation of spatial resolution, and performing the decreased readoutof pixel signals.

1. A color image sensor comprising: a pixel array, in which pixelshaving photoelectric conversion circuits are arranged in rows andcolumns; and a pixel selecting circuit having a row selecting circuitand a column selecting circuit; wherein said pixel selecting circuitselects the pixels of all the rows and/or the pixels of all the columns,and selects a pixel signal at an interval of a plurality of pixels fromamong the selected pixel signals, and outputs the finally selected pixelsignals, the color image sensor further comprising: a plurality ofsample-and-hold circuits, provided at each column, for respectivelysampling and holding pixel signals read out from said pixel array,wherein said row selecting circuit selects each row in said pixel arrayin a predetermined order, and pixel signals of the selected rows areheld in said sample-and-hold circuits, and said column selecting circuitselects and outputs, at intervals of a plurality of columns, pixelsignals which are held in the plurality of sample-and-hold circuits,wherein said pixel array is comprised of RGB pixels, said RGB pixels arearranged in a Bayer Space shape, and said sample-and-hold circuits, fromamong four adjacent rows, hold only R pixel signals from a first row,hold only G pixel signals from second and third rows, and hold only Bpixel signals from a fourth row, and said column selecting circuitsequentially selects said held first and second row R, G pixel signals,and, furthermore, sequentially selects said held third and fourth row G,B pixel signals.
 2. A color image sensor comprising: a pixel array, inwhich pixels having photoelectric conversion circuits are arranged inrows and columns; and a pixel selecting circuit having a row selectingcircuit and a column selecting circuit; wherein said pixel selectingcircuit selects the pixels of all the rows and/or the pixels of all thecolumns, and selects a pixel signal at an interval of a plurality ofpixels from among the selected pixel signals, and outputs the finallyselected pixel signals, the color image sensor further comprising:sample-and-hold circuits, provided at each column, for respectivelysampling and holding pixel signals read out from said pixel array; and agroup of switches, disposed between said pixel array and sample-and-holdcircuits, for suitably selecting said columns, and supplying the pixelsignals to said sample-and-hold circuits, wherein said pixel array iscomprised of RGB pixels, said RGB pixels are arranged in a Bayer Spaceshape, and, when a first row is selected from among four adjacent rowsby said row selecting circuit, said sample-and-hold circuit holds the Rpixel signals by way of a group of switches corresponding to the R pixelsignals, and when a second row is selected, said sample-and-hold circuitholds the G pixel signals by way of a group of switches corresponding tothe G pixel signals, and thereafter mosaic signals in the sequence ofRGRG are sequentially selected and outputted by said column selectingcircuit.
 3. A color image sensor comprising: a pixel array, in whichpixels having photoelectric conversion circuits are arranged in rows andcolumns; a row selecting circuit for selecting pixels in the rowdirection of said pixel array; sample-and-hold circuits, provided ateach column, for respectively sampling and holding pixel signals readout from said pixel array; and a column selecting circuit for selectingpixel signals which said sample-and-hold circuits hold, wherein saidsample-and-hold circuits average pixel signals of the same color, whichare close to one another in the row direction and/or column direction ofsaid pixel array, wherein pixels of a plurality of color are arrayed ina predetermined order in said pixel array; when said row selectingcircuit sequentially selects pixels in a plurality of odd-numbered rows,said sample-and-hold circuits average same-color pixel signals in thecolumn direction, and thereafter, the column selecting circuitsequentially selects the averaged pixel signals from saidsample-and-hold circuits; and when said row selecting circuitsequentially selects pixels in a plurality of even-numbered rows, saidsample-and-hold circuits average same-color pixel signals in the columndirection, and thereafter, the column selecting circuit sequentiallyselects the averaged pixel signals from said sample-and-hold circuits;whereby a first row mosaic signal having a first sequence of saidplurality of colors, and a second row mosaic signal having a secondsequence of said plurality of colors are outputted.
 4. The color imagesensor according to claim 3, wherein pixels of a plurality of colors arearrayed in a predetermined order in said pixel array; when said rowselecting circuit selects pixels in the row direction of said pixelarray, said sample-and-hold circuits average pixel signals from theselected pixels, which are the same color, and are close to one anotherin the row direction; and said column selecting circuit sequentiallyselects and outputs said averaged pixel signals, which saidsample-and-hold circuits hold.
 5. The color image sensor according toclaim 4, wherein said sample-and-hold circuits have holding capacitorsfor holding signals corresponding to pixel signals, and said averagedpixel signals are generated by connecting a plurality of holdingcapacitors in parallel.
 6. The color image sensor according to claim 3,wherein pixels of a plurality of colors are arrayed in a predeterminedorder in said pixel array; aid row selecting circuit sequentiallyselects pixels in a plurality of row directions having the same colorarrangement inside said pixel array, and said sample-and-hold circuits,within the same column, average a first pixel signal when a first rowdirection pixel is selected, and a second pixel signal when a second rowdirection pixel is selected; and said column selecting circuitsequentially selects and outputs said averaged pixel signals, which saidsample-and-hold circuits hold.
 7. The color image sensor according toclaim 6, wherein each of said sample-and-hold circuits has a pluralityof holding capacitors in parallel for holding signals corresponding topixel signals, and signals corresponding to said first pixel signal andsecond pixel signal, respectively, are sequentially held in differentholding capacitors, so that said averaged pixel signals are generated.8. The color image sensor according to claim 3, wherein said pixel arrayhas pixels of a plurality of colors which are arrayed in a predeterminedorder; said sample-and-hold circuits hold pixel signals, which are in aplurality of row directions and in different columns; and said columnselecting circuit selects and outputs pixel signals, which saidsample-and-hold circuits hold, as a first row mosaic signal having afirst sequence of said plurality of colors, and a second row mosaicsignal having a second sequence of said plurality of colors,respectively.
 9. The image sensor according to claim 3, wherein ascanning direction of said row selecting circuit and/or said columnselecting circuit is reversible.